Charge pump voltage generators are largely used in many integrated circuits (ICs) for supplying the ICs at a pre-established voltage VNEG that should remain constant as the current absorbed by the load varies. An example of a common charge pump voltage generator is shown in FIG. 1. The output voltage VNEG is regulated via a comparator COMP that compares it with a stable reference (control) voltage VREF1.
The circuit of FIG. 1 has operating phases in which the pump capacitor CP is charged at a certain supply voltage VDD, alternated with operating phases in which the pump capacitor CP is coupled in anti-parallel manner to the charge tank capacitor CT, that supplies the electronic circuit with a voltage VNEG of opposite sign in respect to the charge voltage VDD. As long as the voltage VNEG is smaller than the voltage VREF1, the pump capacitor CP remains coupled to the supply voltage VDD. When the voltage VNEG exceeds the reference voltage VREF1 the capacitor CP charges the tank capacitor CT when the clock signal CK assumes a logically active value, and is charged anew at the supply voltage VDD when the clock signal CK becomes logically null.
In practice, this loop controls the duty cycle at a constant frequency when the charge current is above a certain threshold that depends upon the supply voltage, the on-resistances RON of the switches SW1 and SW2, the pump capacitance CP and the delay of the feedback line, constituted by the comparator and by the logic gates. TCK being the period of the clock signal CK, and Qmin being the minimum charge transferred from the pump capacitor CP to the tank capacitor CT, the load Iload must absorb a minimum current Imin given by the following equation:
                              I          min                =                              Q            min                                T            CK                                              (        1        )            to switch the switches SW1 and SW2 at each period of the clock signal CK.
If the current Iload is smaller than the value Imin, the charge transferred in a clock period from the capacitor CP to the capacitor CT is larger than that necessary for delivering this current for a clock period. The voltage VNEG does not reach the threshold VREF within the current period and the output of the AND gate remains null for more consecutive clock periods.
This situation is undesirable because it generates switching noise in frequency intervals that should be as free as possible from noise for a correct operation of circuits supplied by the charge pump. Indeed, the switches SW1 and SW2 generate switching noise centered around the frequency of the clock signal, when they switch at each period of the clock signal CK, and at a smaller and smaller frequency if they do not switch for more consecutive clock periods. This consequent low frequency noise may disturb sensitive operation of circuits supplied by the charge pump.
The published patent application US 2002/0105312 to Texas Instruments Inc. discloses a charge pump regulator with adjustable output current. In this device, the charging of the tank capacitor is regulated via switches with different on-resistances. A drawback of this approach is that the switches with low on-resistance occupy a relatively large silicon area.